Wafer fabrication encompasses the manufacturing processes that create a multitude of individual chips in and on the wafer surface. Upon completion, the wafer surface is typically covered with identical areas of patterning, with each area defining a single chip (alternately, termed a "die"). The dies are separated from each other by regions that heretofore contain no circuitry. These areas are commonly referred to as "scribe lines". The scribe line areas will eventually be sawed through to separate the wafer into individual chips.
Wafer fabrication requires a high degree of precision. One mistake can render an individual die or perhaps an entire wafer completely useless. Therefore, as the wafer proceeds through fabrication processing steps, it undergoes a variety of tests and evaluations. Towards the end of the processing, the actual devices within the circuits are more fully characterized, and interconnecting lines which interface to large bonding pads are formed. Bonding pads are provided to interface from the micron or sub-micron device level to a larger area suitable for bonding and test.
The basic equipment for an electrical test of individual dies (i.e., wafer-sort, wafer-test or probe) includes several needle-like probes which are positioned onto the bonding pads, or devices on the die, to apply desired voltage, current and polarities. Each time a given bonding pad is contacted by a probe, conductive metal is typically scraped away such that the very act of testing adversely impacts the individual dies. This hinders the later step of wire bonding to the pads.
Test circuitry can also be formed within individual dies. Its sole purpose is to facilitate testing of the dies on the wafer. Accordingly, this test circuitry takes up significant space within the die which is only used prior to sawing the wafer into individual chips.
It would also be desirable to be able to test a large number of dies on the wafer simultaneously in parallel. This would greatly minimize test time. However, test probes are typically very small, making it difficult to simultaneously test several dies in close proximity on the wafer. It is becoming increasingly difficult to align test probes with reducing geometries and increasing numbers of bonding pads.
It would be desirable to overcome these and other problems associated with electrically testing individual dies.